1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
In recent capacitor elements, there has been a growing tendency to adopt MIM (Metal-Insulator-Metal) capacitor having parasitic resistivity and parasitic capacitance extremely smaller than those of conventional MOS capacitors. Japanese Laid-Open Patent Publication No. 2004-241762 describes a configuration of such MIM capacitor used in a semiconductor device, which has a plurality of strip electrodes aligned in the same longitudinal direction, and are formed in a plurality of interconnect layers provided according to the same design rule, in the same process with the general interconnects. In this configuration, capacitors which make use of insulating films held between the adjacent electrodes as capacitor films, are formed when the ground potential GND and source potential VDD are respectively supplied to the adjacent electrodes.
Japanese Laid-Open Patent Publication No. 2000-252428 describes a configuration of a capacitor circuit which includes a first electrode, a second electrode, and a dielectric held between the first and second electrodes, wherein a plurality of first interconnects which function as the first electrode and a plurality of second interconnects which function as the second electrode are alternately provided side-by-side in the same interconnect layer. The Publication also describes a configuration in which the longitudinal directions of the interconnects in the upper and lower layers are orthogonally aligned.
The MIM capacitors described in Japanese Laid-Open Patent Publication Nos. 2004-241762 and 2000-252428 are configured to make the interconnects function as the electrodes, and make the insulating interlayers function as the capacitor film.
Capacitance of thus-configured MIM capacitor depends on the thickness of the interconnects and capacitor films. The capacitance of the MIM capacitor also depends on geometry of the pattern, such as inter-electrode distance. The thickness of the insulating interlayers and the interconnects may vary in the in-plane direction of the substrate, due to variations in the manufacturing processes such as film growth, and polishing typically by chemical mechanical polishing (CMP). The geometry of the pattern may also vary, typically due to variation in the patterning in the in-plane direction of the substrate. For this reason, there has been a problem in that characteristic values of the element, such as capacitance of the MIM capacitors, may depart from the design value, depending on the location where the elements are formed.